Frank William Bennett 613 Bentley Pl, Fort Collins, Co 80526 (970) 402-9269 bennett78@lpbroadband.net Profile (70% firmware, 30% hardware) o Embedded Linux cross development - PowerPC, ColdFire, MIPS, ARM, AVR32, NIOS2 (4 years) o 'C' programming, Unix/Linux applications (12 years) o Linux drivers: DAQ, SPI, I2C, RTC, timers, RS485, Ethernet, MTD, u-boot, kernel builds o Pentium motherboard design, 8051 system monitor Firmware (2 years) o 4 ASIC teams, Graphic Accelerators, IP creation, Verification, Verilog/PLI/C (8 years) o FPGA/CPLD Verilog, VHDL, Xilinx ISE, Altera quartus/Qsys o ASIC tool development/support, Linux, 'C', Perl, TCL, shell (4 years) o Spyglass, Cadence ConFormal Verification (8 mo) o Computer Graphics Hardware/Firmware (15 years) o US Citizen o current location: Fort Collins, CO o Northern Colorado, Austin, San Diego, Phoenix o W2, independent contractor or full time permanent Education BSEE University of Louisville (G.P.A 2.98) MSEE University of Southern California (G.P.A 3.35) Skills Applications VerilogXL, VCS, cVer, ModelSim, Synopsys DC, Signalscan, SpeedChart, Chrysalis, Debussy, Conformal, Spyglass, Make, Perl, Tcl/Tk, Mercurial, Subversion, CVS, RCS, Linux Apache MySQL PHP, HPUX, csh, ksh, Microsoft Project, Office, Eclipse, 2D/3D Computer Graphics Accelerators, Raster, Calligraphic Displays, Logic Design, OrCad, Protel, PCB123, KiCad Platforms ColdFire, PowerPC, 8051, 6502, x86, PIC, pSOC, Linux, ARM11, AVR32, MIPS, NIOS2, VLIW Languages / IDEs 'C', assembler, Verilog, VHDL, Greenhills, Codewarrior, DENX ELDK, ISE, Quartus/Qsys, Eclipse, Visual Studio Work Experience Verigy Fort Collins, CO 2011 Contractor: Developed embedded 'C' code Firmware for multi-Nios2 Altera Stratix IV fpga based multi-channel SATA SSD tester. The master was Linux based with a DDR, triple speed Ethernet, command and shared memory interface to slave NIOS2 processors. Each slave NIOS processors controlled ASICws SATA IP blocks. My code , running standalone read/write block tests achieved full performance IO ops to SSD drives under test Micro Soft Fort Collins CO, 2010 Contractor: Developed Firmware for Proof of Concept, new product. Design involved 3 IDEs and 3 microprocessors: 6502 assembly, pSOC 'C', assembly, 'C#' test code and Nordic wireless dongle 8051 'C'. Coded and debugged ISRs, schedulers, SPI processor communication, RLE compression and packet formatting. Intellon, Toronto, Ontario, CA 2009 Contractor: Wrote diagnostic test Firmware for embedded ARM11, MAC/PHY, SDRAM Gigabit Ethernet to PowerLine bridge ASIC. Developed C++ tests using CodeWarrior ARM11 compiler to verify various Network on a Chip (NOC) paths are functional using in house Software and Verilog (Synopsys VCS, DVE) simulators. Valco Melton, Cincinnati, OH 2008 Firmware Contractor Evaluated various IDEs, selected Eclipse CodeSourcer M68k IDE for Coldfire MCF5282 firmware project for best Compile, link, C++ Visual debugger and BDM wiggler. Debugged, fixed 3 CPU board prototype H/W bugs, setup makefile, ported/debugged C++ for an Industrial Glue Gun Controller application. Wrote low level, bare board device drivers for EZGUI LCD display, LEDs, keypad polling,flash read/write, Console, RS485, I2C RTC, etc. Debugged Modbus like communications to 4 Cypress pSOC slave controllers each running a dual PID temperature control loop. Avago Technology, Fort Collins, Co 2007 Contractor, Tool Point contact for Conformal Formal ASIC verification of restructuring of customer design for equivalence to original input. Spyglass RTL checking for customer drop quality. Certified proper clock domain handling and DFT ready. Mathegraphics, LLC, Fort Collins, Co 2002-present Owner, contractor Build, setup LCD touch panel Digital Picture Frame Demo on Marvell-Arm develop board including build of u-boot, Linux kernel, drivers and file system. Evaluating setting up Verilog Simulation FPGA SOC, OpenRisc, Micro32 Evaluating speed/size of FPGA SOC, design tools: Xilinx ISE, Lattice ispLever Designed schematic and PCB of LCD, touchscreen expansion card for AVR32 based NGW100. Setup/Administer KuroBox, SOHO NAS storage Network backup Developer open source projects: EDIF2KiCad, KiCad, XML4PCB. Triad Systems Engineering, LLC, Fort Collins, Co 2002-2007 1099 Contractor / Project Manager Technical Lead customer visits, project definition, wrote proposals, Statements of Work, Micro Soft Project schedules, managed team up to 4 engineers. Outsource contract for customers: Advanced Energy Incorporated - System lead Engineer - Smart Front Panel - embedded MCF5213 Coldfire processor. Complete Engineering Reference Spec, F/W â??Câ?? coding, debug, test using Green Hill's Multi IDE and H/W, PCB123 design including RS422, pushbutton, shaft encoder and LCD bus interface utilizing a Xilinx CPLD and test fixture programmed in Verilog/VHDL using ISE, ModelSim tool set. EMCO Flow - Firmware Technical Lead - Vortex Mass Flow Meter as Network Appliance - design PPC MPC5200, Linux, Ethernet, minihttpd, pthreads, uboot, configuration wizard, kernel, root file system, Modbus, Created drivers: SPI LCD / keypad, DAC/ADC SPI codec, MTD, RTC, timers, 420ma, RS485. Created H/W, F/W architecture, engineering specification and design Atrato Inc - Firmware initialization code for MIPS based Vitesse SAS/SATA Port multiplier, part of a JBOD array for a video on demand prototype. Network camera - Verilog FPGA simulation, synthesis, floorplanning and timing Internet Appliance containing 2 megapixel image sensor, H/W JPEG compression, POE and an embedded Linux uP Varian - scoped effort to modernize outdated FPGA, 68000 uP based design Hach - Documented build process for 500k lines of C++, handheld 80188, RTOS, uC/OS, Borland 4.51 ANSI/C++ Compiler and Assembler, windowing, menus, file system and modbus controller Agilent Technology, Fort Collins, Co 2000-2002 Member Technical Staff Coded, tested and supported internal ASIC design toolset. Tools include Verilog parsers, cbmake and database traversal in Perl, C and scripts. Also support external tools : XL/NCVerilog/VCS/PLI, RTL checkers and waveform /design viewers. Porting of internal tools to multi architecture platforms : Linux, HPUX, Coded/tested block composition flow tool for physical layout flow and Pad creation. Hewlett Packard, Fort Collins, Co 1988-2000 Member Technical Staff Member Technical Staff - Designed, tested Dual Pentium motherboard. Also accomplished coding/testing firmware for 8051 System Maintenance controller, assembly language, ISR. Team member for four semi-custom ASIC design cycles. Designed, documented, wrote/tested C, Verilog RTL IP and verification code, synthesized and achieved 100 MHz timing budget for 2D/3D graphics pipeline controller ASICs. Accomplished Hardware Lab productivity, design tools support and new tool evaluations. In particular Cadence Verilog, Debussy, and Synopsys Synthesis tools resources. Wrote PLI support functions. Debugged/enhanced schematic to Verilog translator tool. Microcode team member design, code and test of microcode for high performance i860 graphics workstation. Specifically coded, tested, integrated code for 3D matrix / transformation pipeline. Computer Graphics Enhancement, Camarillo, Ca. 1986-1988 Owner, Consultant Performed firmware changes to effect screen warp transformation for dome spherical projection flight simulation system and alignment. Designed floating point Math Engine with SCSI bus frame buffer for Mister Film, investor. Designed multi function card for IBM PC based product for USPO. Designed IBM/AT based floating point accelerator based on NEC DSP chip. Delivered logic design, microcode and Assembler for EFIS avionics display processor. Interactive Machines, Inc, Westlake Village, Ca 1983-1986 Director Hardware Development Architected next generation product. Designed and tested raster calligraphic mixer for avionics applications. Performed hardware design using TTL, FAST, 10k ECL technologies for world's faster 3D floating point graphics processor, wrote firmware diagnostics, hardware design and wrote software tools in "C" computer graphic processors and digital display generator. Product was extended S100 Bus, 68K SCO Unix based front end, 3D floating point display list, with capability for real time animation, flight simulation and avionic applications. Activities Patents 5,903,485 May 11,1999 Division by a Constant Stock Options Reward for adding Formal Verification to ASIC design flow Interests Linux, flying, USTA tennis team captain