Resume of Frank W Bennett November 2009 613 Bentley Place Fort Collins, Colorado 80526 (970)229-9269(home) (970)402-9269(cell) bennett78@digis.net Technical Skills and Tools: Embedded Firmware, C, ASM, VLIW, PPC, Coldfire, x86, 8051, PIC, MPLAB, Linux, DENX ELDK MCP5200, ARM, MIPS, Greenhills, Eclipse, CodeWarrior, RealView Debugger, RTL coding, synthesis and timing for FPGA/ASICs, Verilog ISE, Synopsys, 2D/3D HArdware/Firmware Computer Graphics, Raster, Calligraphic controllers. Logic Design for TTL, ECL, CMOS, CPLD/EPROM families. OrCad schematic capture, Protel, PCB123, KiCad PCB, VerilogXL, NCSim, VCS, ModelSim, cVer, Synopsys, Primetime, Signalscan, Dve, Speedchart,Chrysalis, Debussy, Conformal, SpyGlass, Make, C, Perl, HTML, Tcl/Tk,Linux, PerForce, Subversion, CVS, RCS, Apache, MySQL, PHP, HPUX, shell scripts, microsoft project, spreadsheets, vi, word processors. From 8/09 to 11/09: Intellon, Toronto, Ontario, Ca Contractor: Diagnostic test Firmware for embedded ARM11, MAC/PHY, SDRAM Ethernet to PowerLine bridge ASIC. Developed C++ tests using CodeWarrior ARM11 compiler to verify various Network on Chip (NOC) paths are functional using in house Software and Verilog (Synosys VCS, DVE) simulators. From 7/08 to 11/08: Valco Melton, Cincinatti, Oh Contractor: Hardware prototype debug and fix, Evaluated, selected Eclipse CodeSourcer M68k IDE for Coldfire MCF5282 firmware project for best Compile, link, C++ Visual debugger and BDM wiggler. Setup makefile, ported C++ for an Industrial Glue Gun Controller application. Wrote low level, bare board device drivers for EZGUI LCD display, LEDs, keypad polling, flash read/write, Console, RS485, I2C RTC, etc. Debugged Modbus like commu- nications to 4 pSOC slave controllers each running a dual PID temperature control loop. From 11/07 to 7/08: Mathegraphics, LLC, Fort Collins, Co Owner, Contractor o Development of LCD, touchscreen expansion card for AVR32 based NGW100. o Setup/Administer KuroBox, SOHO NAS storage Network backup o Developer open source projects: EDIF2KiCad, KiCad and XML4PCB. From 3/07 to 11/07: Avago Technology, Fort Collins, CO Temporary Staff: o Conformal Formal ASIC verification of restructuring of customer design for equivalence to original input. o Sypglass RTL checking for customer drop quality. Certified proper clock domain crossing handling and DFT ready. From 8/02 to 3/07: Triad Systems Engineering, Fort Collins, CO Technical Lead customer visits, project definition, wrote proposals, Statements of Work, MicroSoft Project schedules, team technical lead. Engineering accomplishments: o System lead Engineer embedded MCF5213 Coldfire processor for smart front panel. Complete Engineering Reference Spec, F/W coding, debug, test using GreenHill's Multi IDE and H/W, PCB123 design including RS422, push button, shaft encoder and LCD bus interface utilizing a Xilinx CPLD and test fixture programmed in Verilog/VHDL using ISE, ModelSim tool set. o Firmware technical Lead Vortex Flow Meter ported 68HC16 code to MPC5200, Linux, Ethernet, mini-httpd, pthreads, uboot, configuration wizard, kernel, root file system, Modbus, shared memory, drivers: SPI LCD / keypad, DAC/ADC SPI, I2C, MTD, RTC, timers, 4-20ma, RS485. o Schematic and PCB layout of expansion boards for Processor development boards enabling concurrent firmware development using PCB123 for above projects. o Embedded appliance, Vortex Mass flow meter, coldfire, interviewed customer to create architecture, design and engineering specification. o Firmware initialization for MIPS based Vitesse SAS/SATA Port multiplier, part of a JBOD array for Atrenta video on demand prototype. o Network camera Verilog FPGA simulation, synthesys, floorplanning and timing Internet Appliance containing 2 megapixel image sensor, H/W JPEG compression, POE and an embedded Linux uP o scoped effort to modernize outdated FPGA, uP based design o Documented build process for 500k lines of C++, handheld 80188, RTOS, uC/OS, Borland 4.51 ANSIC/C++ Compiler and Assembler, windowing, menus, file system and modbus controller From 4/00 to 8/02: Agilent Technologies, Fort Collins, Co. Member Technical Staff Code, test and support internal ASIC design toolset. Tools include Verilog parsers, cbmake and database traversal in Perl, C and scripts. Also support external tools such as XL/NCVerilog/VCS/PLI, RTL checkers and waveform /design viewers. Porting of internal tools to multi architecture platforms such as Linux, HPUX. Coded/tested block composition flow tool for physical layout flow and Pad creation. From 6/88 to 04/00: Hewlett Packard, Fort Collins, CO. Member Technical Staff Designed, tested Dual Pentium mother- board. Also accomplished coding/testing firmware for 8051 System Management controller, assembly language, ISR. Team member for four semiCustom ASIC design cycles. Designed, docu- mented, wrote/tested C, Verilog RTL IP, synthesized and achieved 100 Mhz timing budget for 2D/3D graphics pipeline controller ASICs. Contributed and debugged tests in automatic verification test suite, where each block could be configured in RTL, 'C' (PLI) or gates with Revision Control. Accomplished Hardware Lab productivity, design tools support and new tool evaluations. In particular Cadence Verilog, Veritime, and Synopsys Synthesis tools resources. Wrote PLI support functions. Debugged/en- hanced schematic to Verilog translator tool. Microcode team member design, code and test of microcode for high performance i860 graphics workstation. Specifically coded, tested, inte- grated code for 3D matrix / transformation pipeline. From 7/86 to 6/88: Computer Graphics Enhancement, Camarillo, Ca. Owner and Consultant performed firmware changes to effect screen warp transformation for dome spherical projection flight simulation sys tem and alignment. Designed floating point Math Engine with SCSI bus frame buffer for investor. Designed multi function card for IBM PC based product for USPO. Designed IBM/AT based floating point accelerator based on NEC DSP chip. Delivered VLIW logic design, microcode and Assembler for EFIS avionics LCD display processor. From 1/83 to 7/86: Interactive Machines Inc, Westlake Village, Ca Architected next generation product. Designed and tested raster calli- graphic mixer for avionics applications. Performed hardware design using TTL, FAST,10k ECL technologies, wrote firmware diagnostics, hardware design and wrote software tools in "C" computer graphic processors and digital display generator. Product was extended S100 Bus, 68K SCO unix based front end, 3D floating point display list, for real time animation, flight simulation and avionic applications. Patents 5,903,485 May 11,1999 Division by a Constant Stock Options Reward for adding Formal Verification to ASIC design flow Education BSEE University of Louisville (G.P.A 2.98) MSEE University of Southern California (G.P.A 3.35) Interests : Linux, flying, USTA tennis team captain